CS2202 DIGITAL PRINCIPLES AND SYSTEMS DESIGN ANNA UNIVERSITY QUESTION PAPER NOV/DEC 2009 for CSE & IT dpt's...

B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2010

Third Semester

Computer Science and Engineering

CS 2202 â€" DIGITAL PRINCIPLES AND SYSTEMS DESIGN

(Common to Information Technology)

(Regulation 2008)

Time : Three hours Maximum : 100 Marks

Answer ALL questions

PART A â€" (10 × 2 = 20 Marks)

1. Find the octal equivalent of hexadecimal number AB.CD.
2. State and prove the consensus theorem.
3. Compare the serial and parallel adder.
4. Define look ahead carry addition.
5. Define priority encoder.
6. Write a dataflow description of a 2-to-1 line Mux using a conditional operator.
7. Differentiate Moore and Mealy circuit models.
8. What are the applications of shift registers?
9. What is meant by critical race?
10. What are the types of hazards?
PART B â€" (5 × 16 = 80 Marks)11. (a) Simplify the following 5 variable Boolean expression using McCluskey
method.
m F Σ = (0, 1 , 9, 15, 24, 29, 30) + d (8, 11, 31).
Or
(b) Determine the minterm sum of product form of the switching function.
Σ = F (0, 1, 4, 5, 6, 11, 14, 15, 16, 17, 20-22, 30, 32, 33, 36, 37, 48, 49, 52,
53, 59, 63).
12. (a) Realize a BCD to Excess-3 code conversion circuit starting from its truth
table.
Or
(b) Design a full adder and subtractor using NAND and NOR gates
respectively.
13. (a) (i) Define Multiplexer
(ii) Implement the following Boolean function using 8:1 MUX.
F(A, B, C, D) = D C A CD B ACD D B A + + +
Or
(b) Implement the switching functions
de bc e d c b a e d b a z + + + =
1
e c a z =
2 .
bd e d c de bc z + + + =
3
ce e c a z + =
4 using a 5X8X4 programmable logic array.
14. (a) Design a clocked sequential machine using T flip flops for the following
state diagram. Use state reduction if possible. Also use straight binary
state assignment.
Or
(b) Using RS-FFs design a parallel counter which counts in the sequence
000,111, 101, 110, 001, 010, 000.......
15. (a) Design a T flip flop from logic gates.
Or
(b) Find a static and dynamic hazard free realization for the following
function using
(i) NAND gates.
(ii) NOR gates
f(a,b, c, d) = Σm ( 1,5,7,14,15).